The present invention concerns a method of impurity doping into a semiconductor and an apparatus for use in such a method and, more in particular, it relates to a method of impurity doping into a semiconductor and an apparatus for use in such a method suitable to formation of a shallow junction with extremely small diffusion of an impurity distribution.
In silicon integrated circuits, high degree of integration and high operation speed have been attained so far by reducing the size of devices by the miniaturization of fabrication size. According to the scaling law, in order to form a refined MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor), it is necessary for miniaturization in the direction of a plane, as well as reduction in the thickness of the gate oxide film or the direction of depth of a source/drain junction. Heretofore, ion implantation has been used for the formation of the source/drain function. However, for attaining a miniaturized device with a gate length of less than 0.2 .mu.m that completely suppresses a short channel effect, an ultra-shallow junction at a ten nanometer order is required, which is a region difficult to be attained by ion implantation. Therefore, solid phase diffusion from a boron or phosphorus-doped oxide film (BSG, PSG) has been reestimated as a method of forming the shallow junction as described above. For instance, an example of trial production for n channel MOSFET having a gate length of 0.04 .mu.m was reported in 1993 International Electron Devices Meeting, Technical Digest, pp. 119-122, and a source/drain junction at a junction depth of 10 nm, which was impossible to attain by ion implantation, has been attained.
However, in a case of selective doping for complementary MOSFET (CMOS) by the impurity doping method using the solid phase diffusion, it is necessary to previously fabricate a BSG or PSG film in a pattern as a impurity source used in the solid phase diffusion, or mask an undoped region previously with an oxide film before deposition of the BSG or PSG film. As a result, steps such as oxide film deposition and etching are added to the photoresist step to result in a problem that number of steps is further increased as compared with that in ion implantation.
Further, along with miniaturization of devices, an abrupt impurity distribution exceeding the limit of ion implantation is required also to a punch-through stopper formed for suppressing the short channel effect, in addition to the formation of the source/drain junction.
Furthermore, there is a problem of requiring a great number of steps at present, for example, in the well formation for CMOS, and channel doping for controlling various kinds of threshold voltages in memory LSI.